Lattice Semiconductor ISPLSI 3320-100LQ CPLD: Architecture, Features, and System Applications
The Lattice Semiconductor ISPLSI 3320 is a high-density Complex Programmable Logic Device (CPLD) from the mature but highly capable 3000 series family. Fabricated on Lattice's advanced E²CMOS technology, this device represents a significant workhorse in digital logic design, offering a robust blend of programmability, performance, and integration. The -100LQ suffix specifically denotes a 100ns maximum pin-to-pin delay speed grade in a Low-profile Quad Flat Pack (LQFP).
Architecture: A Hierarchical Approach
The architecture of the ISPLSI 3320 is built around a highly flexible, programmable core. Its fundamental structure consists of the following key elements:
Generic Logic Blocks (GLBs): The device contains 32 GLBs, each capable of implementing a significant amount of combinatorial and sequential logic. Each GLB is based on a Programmable AND-Array feeding into a Reconfigurable OR-Array, which then connects to programmable registers. This structure efficiently implements complex logic functions and state machines.
Global Routing Pool (GRP): This is the central nervous system of the CPLD. The GRP is a global programmable interconnect array that routes signals between all the GLBs and the device's input/output pins. This deterministic interconnect scheme ensures predictable timing performance, a key advantage of CPLDs over FPGAs for control-oriented applications.
Programmable I/O Cells: The device features 160 user I/O pins, each housed within a programmable I/O cell. These cells provide flexibility, supporting various interface standards like TTL and LVCMOS. A critical feature is the individual programmable output slew rate control, allowing designers to minimize switching noise in sensitive applications.
Megablock Structure: The GLBs are grouped into larger units called Megablocks. Each Megablock contains 8 GLBs and connects to a dedicated Output Routing Pool (ORP), which manages the routing between the GLBs and the I/O cells, further enhancing the efficiency of the interconnect.
Key Features and Advantages
The ISPLSI 3320-100LQ integrates several features that made it a popular choice for a wide range of applications:
High Logic Density: With 32 GLBs, it offers equivalent gate counts of several thousand, enabling the integration of multiple discrete logic devices into a single chip.
In-System Programmability (ISP): A cornerstone feature, enabled through an IEEE 1149.1 (JTAG) interface. This allows for field upgrades and rapid prototyping without removing the device from its circuit board, drastically reducing development cycles and cost of ownership.
5V Tolerant I/Os: In an era of mixed-voltage systems, its ability to interface with 5V logic levels while potentially being powered by a lower core voltage was a significant system design advantage.
Non-Volatile E²CMOS Technology: The configuration is stored in on-chip non-volatile memory. This means the device instantly becomes active upon power-up, requiring no external boot PROM, simplifying board design and improving reliability.
Predictable Timing Model: The fixed, deterministic interconnect of the CPLD architecture eliminates routing uncertainties, ensuring that pin-to-pin delays are consistent and predictable across designs.
System Applications
The combination of density, non-volatile memory, and predictable timing made the ISPLSI 3320-100LQ ideal for numerous system functions, often serving as a "glue logic" device or a system manager:
Address Decoding and Bus Interface: Generating chip select signals and managing bus arbitration in microprocessor and microcontroller-based systems (e.g., 8051, Motorola 68k).
State Machine Implementation: Perfect for designing complex control logic and finite state machines that require fast, deterministic response times.
Data Path Control and Bridging: Acting as an interface between two subsystems with different protocols or timing requirements, such as between a CPU and a peripheral device.
System Configuration and Power Management: Sequencing the power-up and configuration of other components on the board, such as FPGAs or ASICs.
ICGOOODFIND Summary
The Lattice Semiconductor ISPLSI 3320-100LQ stands as a classic example of a high-performance, high-density CPLD. Its architecture, built around a deterministic interconnect and non-volatile, in-system programmable technology, provided designers with a reliable and flexible solution for integrating complex digital logic, managing system control functions, and bridging interfaces. Its legacy lies in its ability to reduce system component count, improve reliability, and enable rapid design iterations.
Keywords: CPLD, In-System Programmability (ISP), Deterministic Interconnect, Glue Logic, E²CMOS Technology.
